In a semiconductor integrated circuit (IC) fabrication process, the back end of line (BEOL) processing results in interconnects including alternating metal (e.g., copper) and interlayer dielectric (ILD) layers, with vias through the ILD layers connecting the metal layers. With current processes, electrical shorts in interconnects (VxMx) and time dependent dielectric breakdown (TDDB) in conductive vias (Vx) can occur due to charge chamfer angle. Specifically, an interconnect becomes misaligned with the underlying via, causing an overlay, creating a charge chamfer angle. TDDB is the most significant scaling limiter for BEOL and forces manufacturers to use self-aligned double patterning (SADP) lithography. Moreover, another drawback with current processing is ILD damage caused by chemical mechanical polishing (CMP) after metallization and subsequent etch stop layer formation using plasma enhanced chemical vapor deposition (PECVD) to deposit a nitrogen doped carbide (NDC) or silicon carbon nitride (SiCNH or NBlock) diffusion layer. Electron energy loss spectroscopy (EELS) line scan demonstrates that almost 2.5 nanometers (nm) of damage can occur in the ILD after integration which undesirably increases lateral capacitance.
A need therefore exists for improved methodology and an apparatus that reduces the risk of electrical short and ILD damage during semiconductor manufacturing.